1. Field of the Invention
The present invention relates to a semiconductor device having an SOI (Semiconductor On Insulator) structure, and a process for manufacturing same.
2. Description of the Related Art
Heretofore, various structures for isolating elements in a semiconductor chip have been proposed, to separate power elements such as a DMOS transistor and a CMOS transistor when composing a control or logic part, and an example thereof is described in Japanese Unexamined Patent Publication (Kokai) No. 62-76645. As illustrated in FIG. 1, two wafers, i.e., a first semiconductor substrate 100 and a second semiconductor substrate 101, are bonded with an insulating layer 102 inserted therebetween. The first semiconductor substrate 100, insulating layer 102, and second semiconductor substrate 101 are locally etched, in this order, to expose a part of the second semiconductor substrate 101, an epitaxial layer 103 is formed on the exposed second semiconductor substrate 101 at the etched part, and a DMOS transistor is formed in the epitaxial layer 103. To isolate the remaining part of the first semiconductor substrate 100 other than the etched part, an isolation element 104 is formed by the trench technique.
The reason why the structure of "the epitaxial layer on the exposed second semiconductor substrate 101 at the etched part" is adopted, although the cost of this structure is high, is that the first semiconductor substrate 100 can be ground after the bonding of the wafers, but the first semiconductor substrate 100, i.e., an SOI layer, cannot be made thin due to a large dispersion of the thickness, typically .+-.5.0 .mu.m, when polished by a conventional polishing method. Accordingly, the first semiconductor substrate 100 or polished SOI layer is, for example, 20 .mu.m thick, in Japanese Unexamined Patent Publication (Kokai) No. 62-76645, and therefore, the etched part has a deep step such as 20 .mu.m, which prevents a later formation of an element on the exposed second semiconductor substrate. The reason why the structure of "an element isolation 104 formed by the trench technique" is adopted is similar. Namely, since the SOI layer is as thick as 20 .mu.m, a deep step is formed if an island isolation is adopted, and the deep step prevents the formation of another element. Further, the steps of the epitaxial growth and trench isolation processes are complex, and a large number of process steps is required, thereby further increasing costs.
Recently, the polishing technique has been improved and a dispersion of a layer thickness after polishing can be reduced to about .+-.0.5 .mu.m, which allows a semiconductor substrate to be polished to a considerably thin thickness. The limit of a focusing depth of an alignment device is currently 6 .mu.m, and a layer island having a step height of 6 .mu.m can be planarized by the use of the TEOS (Tetra Ethyl Ortho-Silicate) layer or SOG (Spin On Glass) layer technique. Accordingly, in consideration of the above prior art, the inventors manufactured a semiconductor device having a semiconductor layer (SOI layer) less than 6 .mu.m thick, on an insulating layer. By reducing the thickness of the SOI layer to less than 6 .mu.m, a height of a step formed when isolated by an island isolation is so low that an epitaxial layer is not necessary, and trench forming is not necessary because of the island isolation or a time required for the trench forming step is shortened even if an isolation trench must be formed, which improves the productivity.
Nevertheless, a problem has been found during the investigation and development of the above semiconductor devices. This problem did not arise in the prior art because of a thick thickness of an SOI layer, but it appears that the characteristics of an semiconductor element are deteriorated when the thickness of an SOI layer is made less than 6 .mu.m and an insulating gate type field effect transistor such as an MOS transistor is formed in the SOI layer. This is explained with reference to FIGS. 2A and 2B. FIG. 2A shows a section of an MOS transistor formed on the SOI layer, and FIG. 2B shows the impurity concentration profile of a section cut along the line A--A of FIG. 2A. In FIG. 2A, an N-type SOI layer 201 having a thickness of less than 6 .mu.m is formed on a field oxide layer 200, a P.sup.- -type region 202 is formed by introducing a P-type impurity into the N-type SOI layer 201 from the surface thereof, source and drain regions 203 and 204 are formed in the P.sup.- -type region 202, and a gate electrode 205 is formed on an insulating layer above the SOI layer 201. The P-type impurity does not reach the bottom of the SOI layer 201, and therefore, a portion adjacent to the bottom remains N-type and an NPN-type parasitic transistor is formed from an N.sup.- -type region 206 between the P.sup.- -type region 202 and the source region 203, since a distance between the N -type region 206 and the source region 203 is short due to a thin thickness of the SOI layer 201. This parasitic transistor, however, causes a current leakage when the MOS transistor is in a cut-off state.
Therefore, the object of the present invention is to provide a semiconductor device having an SOI structure in which a thickness of a semiconductor region of a single crystal formed on an insulating layer is made thinner, and the characteristics of an element formed in the semiconductor region are improved, and a process for manufacturing such a semiconductor device.